View MAX17030GTL_4467927.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-4577; Rev 0; 4/09
KIT ATION EVALU BLE AVAILA
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
General Description Features
o Triple/Dual-Phase Quick-PWM Controllers o 2 Internal Drivers + 1 External Driver o 0.5% VOUT Accuracy Over Line, Load, and Temperature o 7-Bit IMVP-6.5 DAC o Dynamic Phase Selection Optimizes Active/Sleep Efficiency o Transient Phase Overlap Reduces Output Capacitance o Transient Suppression Feature (MAX17036 Only) o Integrated Boost Switches o Active Voltage Positioning with Adjustable Gain o Accurate Lossless Current Balance and Current Limit o Remote Output and Ground Sense o Adjustable Output Slew-Rate Control o Power-Good (IMVPOK), Clock Enable (CLKEN), and Thermal-Fault (VRHOT) Outputs o IMVP-6.5 Power Sequencing and Timing Compliant o Output Current Monitor (IMON) o Drives Large Synchronous Rectifier FETs o 7V to 26V Battery Input Range o Adjustable Switching Frequency (600kHz max) o Undervoltage, Overvoltage, and Thermal-Fault Protection
MAX17030/MAX17036
The MAX17030/MAX17036 are 3/2-phase interleaved Quick-PWMTM step-down VID power-supply controllers for IMVP-6.5 notebook CPUs. Two integrated drivers and the option to drive a third phase using an external driver such as the MAX8791 allow for a flexible 3/2-phase configuration depending on the CPU being supported. True out-of-phase operation reduces input ripple-current requirements and output-voltage ripple while easing component selection and layout difficulties. The QuickPWM control provides instantaneous response to fast load-current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX17030/MAX17036 are intended for bucking down the battery directly to create the core voltage. The single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. An output current monitor provides an analog current output proportional to the sum of the inductor currents, which in steady state is the same as the current consumed by the CPU.
Applications
IMVP-6.5 SV and XE Core Power Supplies High-Current Voltage-Positioned Step-Down Converters 3 to 4 Li+ Cells Battery to CPU Core Supply Converters Notebooks/Desktops/Servers
Pin Configuration
BST1 BST2 20 PWM3 19 DRSKP 18 PWRGD 17 CLKEN 16 TON 15 PSI 14 DPRSLPVR 13 SHDN 12 CSP2 11 CSN2 1 CSN3 2 CSP3 3 THRM 4 IMON 5 ILIM 6 TIME 7 VCC 8 FB 9 FBAC 10 GNDS DH1 DH2 DL1 DL2 VDD LX1 LX2
TOP VIEW
30 29 28 27 26 25 24 23 22 21 PGD_IN 31
Ordering Information
PART MAX17030GTL+ MAX17036GTL+ TEMP RANGE -40C to +105C -40C to +105C PIN-PACKAGE 40 TQFN-EP* 40 TQFN-EP*
D0 32 D1 33 D2 34 D3 35 D4 36 D5 37 D6 38 CSP1 39 CSN1 40
MAX17030 MAX17036
+Denotes a lead-free(Pb)/RoHS-compliant package. *EP = Exposed pad.
+
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
THIN QFN 5mm x 5mm
________________________________________________________________ Maxim Integrated Products
VRHOT
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
ABSOLUTE MAXIMUM RATINGS
(Note 1) VCC, VDD to GND .....................................................-0.3V to +6V D0-D6, PGD_IN, PSI, DPRSLPVR to GND ...............-0.3V to +6V CSP_, CSN_, THRM, ILIM to GND............................-0.3V to +6V PWRGD, CLKEN, VR_HOT to GND..........................-0.3V to +6V FB, FBAC, IMON, TIME to GND .................-0.3V to (VCC + 0.3V) SHDN to GND (Note 2)...........................................-0.3V to +30V TON to GND ...........................................................-0.3V to +30V GNDS to GND .......................................................-0.3V to +0.3V DL1, DL2, PWM3, DRSKP to GND .............-0.3V to (VDD + 0.3V) BST1, BST2 to GND ...............................................-0.3V to +36V BST1, BST2 to VDD .................................................-0.3V to +30V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) Continuous Power Dissipation (40-pin, 5mm x 5mm TQFN) Up to +70C ..............................................................1778mW Derating above +70C ..........................................22.2mW/C Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10s) .................................+300C
Note 1: Absolute Maximum Ratings valid using 20MHz bandwidth limit. Note 2: SHDN might be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Internal BST switches are disabled as well. Use external BST diodes when SHDN is forced to 12V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PWM CONTROLLER Input Voltage Range VCC, VDD VIN Measured at FB with respect to GNDS; includes loadregulation error (Note 3) DAC codes from 0.8125V to 1.5000V DAC codes from 0.3750V to 0.8000V DAC codes from 0 to 0.3625V 4.5 7 -0.5 -7 -20 1.094 VCC = 4.5V to 5.5V, VIN = 4.5V to 26V TA = +25C A GNDS IGNDS VTIME VOUT/ VGNDS TA = +25C RTIME = 147k RTIME = 147k (6.08mV/s nominal) RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) Soft-start and soft-shutdown: RTIME = 35.7k (6.25mV/s nominal) to 178k (1.25mV/s nominal) -0.1 -200 0.97 -0.5 1.985 -10 -15 2.000 1.00 1.100 0.1 +0.1 +200 1.03 +0.5 2.015 +10 +15 % -20 +20 5.5 26 +0.5 +7 mV +20 1.106 V % A mV V/V A V V % SYMBOL CONDITIONS MIN TYP MAX UNITS
FB Output Voltage Accuracy
VFB
Boot Voltage Line Regulation Error FB Input Bias Current GNDS Input Range GNDS Gain GNDS Input Bias Current TIME Regulation Voltage
VBOOT
TIME Slew-Rate Accuracy
2
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL VIN = 10V, VFB = 1.0V, measured at DH1, DH2, and PWM3 (Note 4) CONDITIONS RTON = 96.75k (600kHz per phase), 167ns nominal RTON = 200k (300kHz per phase), 333ns nominal RTON = 303.25k (200kHz per phase), 500ns nominal MIN -15 -10 -15 300 0.01 TYP MAX +15 +10 +15 375 0.1 ns A % UNITS
MAX17030/MAX17036
On-Time Accuracy
t ON
Minimum Off-Time TON Shutdown Input Current BIAS CURRENTS Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) FAULT PROTECTION
t OFF(MIN) ITON,SDN
Measured at DH1, DH2, and PWM3 (Note 4) SHDN = GND, VIN = 26V, VCC = VDD = 0 or 5V, TA = +25C Measured at VCC, VDPRSLPVR = 5V, FB forced above the regulation point Measured at VDD, VDPRSLPVR = 0, FB forced above the regulation point, TA = +25C Measured at VCC, SHDN = GND, TA = +25C Measured at VDD, SHDN = GND, TA = +25C Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at FB Minimum OVP threshold; measured at FB
ICC IDD ICC,SDN IDD,SDN
3.5 0.02 0.01 0.01
7 1 1 1
mA A A A
250
300
350
mV
Output Overvoltage-Protection Threshold
VOVP
1.45
1.50 0.8 10
1.55
V
Output OvervoltagePropagation Delay Output UndervoltageProtection Threshold Output UndervoltagePropagation Delay CLKEN Startup Delay and Boot Time Period
t OVP VUVP tUVP tBOOT
FB forced 25mV above trip threshold Measured at FB with respect to the voltage target set by the VID code (see Table 4) FB forced 25mV below trip threshold Measured from the time when FB reaches the boot target voltage (Note 3) 20 -450
s -350 mV s 100 s
-400 10 60
_______________________________________________________________________________________
3
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PWRGD Startup Delay SYMBOL CONDITIONS Measured at startup from the time when CLKEN goes low Measured at FB with respect to the voltage target set by the VID code (see Table 4), 20mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) MIN 3 TYP 6.5 MAX 10 UNITS ms
-350
-300
-250 mV
CLKEN and PWRGD Threshold
+150
+200
+250
CLKEN and PWRGD Delay CLKEN and PWRGD Transition Blanking Time (VID Transitions) CLKEN, PWRGD Output Low Voltage CLKEN, PWRGD Leakage Current CSN1 Pulldown Resistance in UVLO and Shutdown VCC Undervoltage-Lockout Threshold THERMAL PROTECTION VRHOT Trip Threshold VRHOT Delay VRHOT Output On-Resistance VRHOT Leakage Current THRM Input Leakage Thermal-Shutdown Threshold ITHRM T SHDN t VRHOT VUVLO(VCC) tBLANK
FB forced 25mV outside the PWRGD trip thresholds Measured from the time when FB reaches the target voltage (Note 3) Low state, I SINK = 3mA High-Z state, pin forced to 5V, TA = +25C SHDN = GND, measured after softshutdown completed (DL = low) Rising edge, 65mV typical hysteresis, controller disabled below this level 4.05
10 20 0.4 1 8 4.27 4.48
s s V A
V
Measured at THRM with respect to VCC; falling edge, typical hysteresis = 75mV THRM forced 25mV below the VRHOT trip threshold, falling edge High-Z state, VRHOT forced to 5V, TA = +25C VTHRM = 0 to 5V, TA = +25C Typical hysteresis = 15C VTIME - VILIM = 100mV VLIMIT VCSP_ - VCSN_ VTIME - VILIM = 500mV ILIM = VCC
29
30 10 2
31
% s
RON(VRHOT) Low state -0.1
8 1 +0.1 A A C 13 55 25 +4 mV mV 2 V mV
+160 7 45 20 -4 0 0 10 50 22.5
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive) Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) CSP_, CSN_ Common-Mode Input Range
VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT VZX VGND - VLX_, VDPRSLPVR = 5V
4
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Phases 2, 3 Disable Threshold CSP_, CSN_ Input Current ILIM Input Current ICSP, ICSN I ILIM SYMBOL CONDITIONS Measured at CSP2, CSP3 TA = +25C TA = +25C (1/N) x (VCSP_ VCSN_) at IFBAC = 0; TA = +25C indicates summation over all power-up enabled phases from 1 to N, TA = 0C to +85C N=3 IFBAC/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VFBAC = VCSN_ = 0.45V to 1.5V (1/N) x (VCSP_ - VCSN_) at I IMON = 0, indicates summation over all power-up enabled phases from 1 to N, N = 3 I IMON/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VCSN_ = 0.45V to 1.5V MIN 3 -0.2 -0.1 -0.5 TYP VCC 1 MAX VCC 0.4 +0.2 +0.1 +0.5 mV/ phase -0.75 +0.75 UNITS V A A
MAX17030/MAX17036
Droop Amplifier Offset
Droop Amplifier Transconductance
Gm(FBAC)
393
400
406
S
Current-Monitor Offset
-1.1
+1
mV/ phase
Current-Monitor Transconductance GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance DH_ Gate-Driver Source Current DH_ Gate-Driver Sink Current DL_ Gate-Driver Source Current DL_ Gate-Driver Sink Current DL_ Transition Time DH_ Transition Time Internal BST_ Switch On-Resistance
Gm(IMON)
1.552
1.6
1.648
mS
R ON(DH) R ON(DL)
BST_ - LX_ forced to 5V
High state (pullup) Low state (pulldown) High state (pullup) Low state (pulldown)
0.9 0.7 0.7 0.25 2.2 2.7 2.7 8 20 20 20 20 10
2.5 2 2 0.7 A A A A ns ns 20
DH_ forced to 2.5V, IDH(SOURCE) BST_ - LX_ forced to 5V IDH(SINK) DH_ forced to 2.5V, BST_ - LX_ forced to 5V DL_ forced to 2.5V DL_ falling, CDL_ = 3nF DL rising, CDL_ = 3nF DH_ falling, CDH_ = 3nF DH_ rising, CDH_ = 3nF R ON(BST) IBST_ = 10mA
IDL(SOURCE) DL_ forced to 2.5V IDL(SINK)
_______________________________________________________________________________________
5
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER PWM3, DRSKP OUTPUTS PWM3, DRSKP Output High Voltages PWM3, DRSKP Output Low Voltages LOGIC AND I/O Logic-Input High Voltage Logic-Input Low Voltage Low-Voltage Logic-Input High Voltage Low-Voltage Logic-Input Low Voltage Logic Input Current VIH VIL VIHLV VILLV SHDN, PGD_IN SHDN, PGD_IN PSI, D0-D6, DPRSLPVR PSI, D0-D6, DPRSLPVR TA = +25C; SHDN, DPRSLPVR, PGD_IN, PSI, D0-D6 = 0 or 5V -1 0.67 0.33 +1 2.3 1.0 V V V V A I SOURCE = 3mA I SINK = 3mA VDD 0.4V 0.4 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = -40oC to +105C, unless otherwise noted.) (Note 5)
PARAMETER PWM CONTROLLER Input Voltage Range VCC, VDD VIN Measured at FB with respect to GNDS, includes loadregulation error (Note 3) DAC codes from 0.8125V to 1.5000V DAC codes from 0.3750V to 0.8000V DAC codes from 0 to 0.3625V 4.5 7 -0.75 -10 -25 1.085 -200 A GNDS VTIME VOUT/ VGNDS RTIME = 147k RTIME = 147k (6.08mV/s nominal) RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) Soft-start and soft-shutdown: RTIME = 35.7k (6.25mV/s nominal) to 178k (1.25mV/s nominal) 0.95 1.985 -10 -15 5.5 26 +0.75 +10 mV +25 1.115 +200 1.05 2.015 +10 +15 % -20 +20 V mV V/V V V % SYMBOL CONDITIONS MIN TYP MAX UNITS
FB Output-Voltage Accuracy
VFB
Boot Voltage GNDS Input Range GNDS Gain TIME Regulation Voltage
VBOOT
TIME Slew-Rate Accuracy
6
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = -40oC to +105C, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL VIN = 10V, VFB = 1.0V, measured at DH1, DH2, and PWM3 (Note 4) CONDITIONS RTON = 96.75k (600kHz per phase), 167ns nominal RTON = 200k (300kHz per phase), 333ns nominal RTON = 303.25k (200kHz per phase), 500ns nominal MIN -15 -10 -15 TYP MAX +15 +10 +15 400 ns % UNITS
MAX17030/MAX17036
On-Time Accuracy
t ON
Minimum Off-Time BIAS CURRENTS Quiescent Supply Current (VCC) FAULT PROTECTION
t OFF(MIN)
Measured at DH1, DH2, and PWM3 (Note 4) Measured at VCC, DPRSLPVR = 5V, FB forced above the regulation point
ICC
7
mA
Output Overvoltage-Protection Threshold
VOVP
Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to the voltage target set by the VID code (see Table 4) Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at FB
250
350
mV
1.45
1.55
V
Output Undervoltage-Protection Threshold CLKEN Startup Delay and Boot Time Period PWRGD Startup Delay
VUVP tBOOT
Measured at FB with respect to the voltage target set by the VID code (see Table 4) Measured from the time when FB reaches the boot target voltage (Note 3) Measured at startup from the time when CLKEN goes low Measured at FB with respect to the voltage target set by the VID code (see Table 4), 20mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage)
-450 20 3
-350 100 10
mV s ms
-350
-250 mV
CLKEN and PWRGD Threshold
+150
+250
CLKEN, PWRGD Output Low Voltage VCC Undervoltage-Lockout Threshold THERMAL PROTECTION VRHOT Trip Threshold VRHOT Output On-Resistance VUVLO(VCC)
Low state, I SINK = 3mA Rising edge, 65mV typical hysteresis, controller disabled below this level 4.05
0.4 4.5
V V
Measured at THRM with respect to VCC, falling edge, typical hysteresis = 75mV RON(VRHOT) Low state
29
31 8
%
_______________________________________________________________________________________
7
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57k from FBAC to CSN_, [D6-D0] = [0101000]; TA = -40oC to +105C, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS VTIME - VILIM = 100mV VLIMIT VCSP_ - VCSN_ VTIME - VILIM = 500mV ILIM = VCC Current-Limit Threshold Voltage (Negative) Accuracy CSP_, CSN_ Common-Mode Input Range Phases 2, 3 Disable Threshold Measured at CSP2, CSP3 (1/N) x (VCSP_ - VCSN_) at IFBAC = 0; indicates summation over all power-up enabled phases from 1 to N, N = 3 IFBAC/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VFBAC = VCSN_ = 0.45V to 1.5V (1/N) x (VCSP_ - VCSN_) at IFBAC = 0; indicates summation over all power-up enabled phases from 1 to N, N = 3 Gm(IMON) IIMON/ [ (VCSP_ - VCSN_)]; indicates summation over all power-up enabled phases from 1 to N, N = 3, VCSN_ = 0.45V to 1.5V BST_ - LX_ forced to 5V High state (pullup) Low state (pulldown) VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT MIN 7 45 20 -4 0 3 TYP MAX 13 55 25 +4 2 VCC 0.4 +1 mV V V mV/ phase mV UNITS
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR Current-Limit Threshold Voltage (Positive)
Droop Amplifier Offset
-1
Droop Amplifier Transconductance
Gm(FBAC)
390
407
S
Current-Monitor Offset
-1.5
+1.5
mV/ phase
Current-Monitor Transconductance GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance Internal BST_ Switch On-Resistance PWM3, DRSKP OUTPUTS PWM3, DRSKP Output High Voltages PWM3, DRSKP Output Low Voltages LOGIC AND I/O Logic-Input High Voltage Logic-Input Low Voltage Low-Voltage Logic-Input High Voltage Low-Voltage Logic-Input Low Voltage
1.536
1.664
mS
R ON(DH) R ON(DL) R ON(BST)
2.5 2 2 0.7 20
High state (pullup) Low state (pulldown) IBST- = 10mA
I SOURCE = 3mA I SINK = 3mA
VDD 0.4V 0.4
V V
VIH VIL VIHLV VILLV
SHDN, PGD_IN SHDN, PGD_IN PSI, D0-D6, DPRSLPVR PSI, D0-D6, DPRSLPVR
2.3 1.0 0.67 0.33
V V V V
8
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
Note 3: The equation for the target voltage VTARGET is: VTARGET = The slew-rate-controlled version of VDAC, where VDAC = 0 for shutdown VDAC = VBOOT during IMVP-6.5 startup VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 4). In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit times might be different due to MOSFET switching speeds. Note 5: Specifications to -40C and +105C are guaranteed by design, not production tested.
MAX17030/MAX17036
Typical Operating Characteristics
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 0.95V, TA = +25C, unless otherwise specified.)
EFFICIENCY vs. LOAD CURRENT (VOUT(HFM) = 0.95V)
MAX17030 toc01
OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(HFM) = 0.95V)
MAX17030 toc02
EFFICIENCY vs. LOAD CURRENT (VOUT(LFM) = 0.875V)
7V
MAX17030 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0.1 1 10 20V 12V 7V
1.00
90
OUTPUT VOLTAGE (V)
0.95 EFFICIENCY (%)
80 12V 70 20V 60 SKIP MODE PWM MODE
0.90
0.85
0.80 100 0 10 20 30 40 50 60 70 LOAD CURRENT (A) LOAD CURRENT (A)
50 0.1 1 10 100 LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT(LFM) = 0.875V)
MAX17030 toc04
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17030 toc05
VOUT(HFM) = 0.95V NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
DPRSLPVR = VCC DPRSLPVR = GND
MAX17030 toc06
0.90 0.89 OUTPUT VOLTAGE (V) 0.88 0.87 0.86 0.85 0.84 0.83 0 5 10 LOAD CURRENT (A) 15 2-PHASE PWM MODE 1-PHASE SKIP MODE
400 350 SWITCHING FREQUENCY (kHz) 300 250 200 150 100 50 0 DPRSLPVR = VCC DPRSLPVR = GND VOUT(LFM) = 0.875V VOUT(HFM) = 0.95V
1000 IIN ICC + IDD 10 ICC + IDD
100 SUPPLY CURRENT (mA)
1 IIN
0.1
0.01 0 10 20 30 40 50 6 9 12 15 18 21 LOAD CURRENT (A) INPUT VOLTAGE (V)
20
_______________________________________________________________________________________
9
1/2/3-Phase-Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 0.95V, TA = +25C, unless otherwise specified.)
CURRENT BALANCE vs. LOAD CURRENT
20 VOUT = 0.95V SENSE VOLTAGE DIFFERENCE (mV) VCSP1 - VCSN1 SENSE VOLTAGE (mV) 15 VCSP3 VCSN3 10 VCS2 - VCS1 0 VCSP2 - VCSN2 5 -0.1 0.1 80
MAX17030 toc07
IIMON vs. LOAD CURRENT
VOUT = 0.95V
MAX17030 toc08
0.2
100
IMON (A)
60 DPRSLPVR = GND 40
20
0 0 10 20 30
VCS3 - VCS1 40 50 60 70
-0.2
0 0 10 20 30 40 50 60
VCSP - CSN (mV)
LOAD CURRENT (A)
0.8125V OUTPUT VOLTAGE DISTRIBUTION
MAX17030 toc09
Gm(FB) TRANSCONDUCTANCE DISTRIBUTION
+85C +25C SAMPLE SIZE = 100
MAX17030 toc10
70 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 0.8075 0.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175 0 +85C +25C SAMPLE SIZE = 100
70 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 390 392 394 396 398 400 402 404 406 408 410 0
OUTPUT VOLTAGE (V)
TRANCONDUCTANCE (s)
Gm(IMON) TRANSCONDUCTANCE DISTRIBUTION
SAMPLE SIZE = 100 35 SAMPLE PERCENTAGE (%) 30 25 20 15 10 5 1550 1560 1570 1580 1590 1600 1610 0 +85C +25C 1620 1630 1640 1650
MAX17030 toc11
40
TRANCONDUCTANCE (s)
10
______________________________________________________________________________________
1/2/3-Phase-Quick-PWM IMVP-6.5 VID Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0-D6 set for 0.95V, TA = +25C, unless otherwise specified.)
SOFT-START WAVEFORM (UP TO CLKEN)
MAX17030 toc12
MAX17030/MAX17036
SOFT-START WAVEFORM (UP TO PWRGD)
MAX17030 toc13
3.3V 0 3.3V 0 0.95V
A B C
3.3V 0 3.3V 0 3.3V 0 0.95V
A B C D
0 0 0 0 200s/div A. SHDN, 5V/div B. CLKEN, 10V/div C. VOUT, 500mV/div D. ILX1, 10A/div E. ILX2, 10A/div F. ILX3, 10A/div IOUT, 15A A. SHDN, 5V/div B. CLKEN, 6.6V/div C. PWRGD, 10V/div D. VOUT, 1V/div D E F 0 0 0 0 1ms/div E. DL1, 10V/div F. DL2, 10V/div G. DL3, 10V/div IOUT, 15A
E F G
SHUTDOWN WAVEFORM
MAX17030 toc14
LOAD-TRANSIENT RESPONSE (HFM MODE)
MAX17030 toc15
3.3V 0 3.3V 0 3.3V 0 0.95V
A B C
59A A 7A 0.935V
D 0 0 0 0 200s/div A. SHDN, 5V/div B. PWRGD, 10V/div C. CLKEN, 10V/div D. VOUT, 500mV/div E. DL1, 10V/div F. DL2, 10V/div G. DL3, 10V/div 20s/div A. IOUT = 7A - 59A B. VOUT, 50mV/div C. ILX1, 20A/div D. ILX2, 20A/div E. ILX3, 20A/div E F G 0.84V
B
C D E
______________________________________________________________________________________
11
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Pin Description
PIN 1 NAME CSN3 FUNCTION Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. To disable phase 3, connect CSP3 to VCC and CSN3 to GND. Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of VCC) at the desired high temperature. Current Monitor Output Pin. The output current at this pin is: I IMON = GM(IMON) x 4 IMON V(CSP_,CSN_) where GM(IMON) = 1.6mS typical and denotes summation over all enabled phases. An external resistor RIMON between IMON and GNDS sets the current-monitor output voltage: VIMON = ILOAD x R SENSE x GM(IMON) x RIMON where RSENSE is the value of the effective current-sense resistance. Choose RIMON such that VIMON does not exceed 900mV at the maximum expected load current IMAX. IMON is high impedance when the MAX17030/MAX17036 are in shutdown. Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The valley negative current-limit thresholds are typically -125% of the corresponding valley positive current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of 22.5mV typ. Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate: Slew rate = (12.5mV/s) x (71.5k /RTIME) 6 TIME where RTIME is between 35.7k and 178k . This "normal" slew rate applies to transitions into and out of the low-power pulse-skipping modes and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew rate defined above. Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1F minimum. Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator (slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum of the inductor currents is essential for cycle-by-cycle stability. The external connections and compensation at FB depend on the desired DC and transient (AC) droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through capacitor C, where the R x C time constant should be at least 3x the switching period per phase.
2
CSP3
3
THRM
5
ILIM
7
VCC
8
FB
12
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
Pin Description (continued)
PIN NAME FUNCTION Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor RFBAC between FBAC and the positive side of the feedback remote sense to set the transient (AC) droop based on the stability, load-transient response, and voltage-positioning gain requirements: RFBAC = RDROOP,AC/[RSENSE x Gm(FBAC)] where RDROOP,AC is the transient (AC) voltage-positioning slope that provides an acceptable tradeoff between stability and load-transient response, Gm(FBAC) = 400S typ, and RSENSE is the effective current-sense resistance that is used to provide the (CSP_, CSN_) current-sense voltages. A minimum RDROOP,AC value is required for stability, but if there are no ceramic output capacitors used, then the minimum requirement applies to RESR + RDROOP,AC, where RESR is the effective ESR of the output capacitors. If lossless sensing (inductor DCR sensing) is used, use a thermistor-resistor network to minimize the temperature dependence of the voltage-positioning slope. FBAC is high impedance in shutdown. Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. To disable phase 2, connect CSP2 to VCC and CSN2 to GND. Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the IC into the 1A (max at TA = +25C) shutdown state. During startup, the output voltage is ramped up at 1/4 the slew rate set by the TIME resistor to the boot voltage or to the target voltage. During the transition from normal operation to shutdown, the output voltage is ramped down at 1/6 the slew rate set by the TIME resistor. Forcing SHDN to 11V~13V to enter no-fault test mode clears the fault latches, disables transient phase overlap, and turns off the internal BST_-to-VDD switches. However, internal diodes still exist between BST_ and VDD in this state. Deeper Sleep VR Control Input. This low-voltage logic input indicates power usage and sets the operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the controller is immediately set to 1-phase automatic pulse-skipping mode. The controller returns to forcedPWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. During this blanking period, the overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.5V threshold. The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes. DPRSLPVR 1 0 0 PSI X 0 1 MODE Very low current (1-phase skip) Intermediate power potential (N-1-phase PWM) Max power potential (full-phase PWM: N-phase or 1 phase as set by user at CSP2, CSP3)
MAX17030/MAX17036
9
FBAC
10
GNDS
11
CSN2
12
CSP2
13
SHDN
14
DPRSLPVR
______________________________________________________________________________________
13
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Pin Description (continued)
PIN NAME FUNCTION This low-voltage logic input indicates power usage and sets the operating mode together with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase forced-PWM mode when PSI is forced high. The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes. DPRSLPVR 1 0 0 PSI X 0 1 MODE Very low current (1-phase skip) Intermediate power potential (N-1-phase PWM) Max power potential (full-phase PWM: N-phase or 1 phase as set by user at CSP2, CSP3)
15
PSI
Switching Frequency Setting Input. An external resistor between the input power source and this pin sets the switching frequency according to the following equation: f SW = 1/(CTON x (RTON + 6.5k )) 16 TON where CTON = 16.26pF. The external resistor must also satisfy the requirement [VIN(MIN)/RTON] the minimum VIN value expected in the application. TON is high impedance in shutdown. 10A where VIN(MIN) is
17
CLKEN
Clock Enable CMOS Push-Pull Logic Output Powered by V3P3. This inverted logic output indicates when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an additional 20s after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The CLKEN upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transitionrelated PWRGD blanking period is complete and the output reaches regulation. Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and powerdown, if FB is in regulation, then PWRGD is high impedance. PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes high if FB is within the PWRGD threshold window. PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced high impedance for an additional 20s after the transition is completed. The PWRGD upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period is complete and the output reaches regulation. A pullup resistor on PWRGD causes additional finite shutdown current. Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skipmode driver IC. DRSKP swings from VDD to GND. When DRSKP is high, the driver ICs operate in forced-PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and operate in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence, instructing the external drivers to shut down.
18
PWRGD
19
DRSKP
14
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
Pin Description (continued)
PIN 20 NAME PWM3 FUNCTION PWM Signal Output for Phase 3. Swings from GND to VDD. Three-state whenever phase 3 is disabled (in shutdown, when CSP3 is connected to VCC, and when operating with fewer than all phases). Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 highside gate driver. An internal switch between VDD and BST2 charges the BST2-LX2 flying capacitor while the low-side MOSFET is on (DL2 pulled high). Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also used as an input to phase 2's zero-crossing comparator. Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. Phase 2 Low-Side Gate-Driver Output. DL2 swings from GND to VDD. DL2 is forced low in shutdown. DL2 is forced high when an output overvoltage fault is detected, overriding any negative currentlimit condition that might be present. DL2 is forced low in skip mode after detecting an inductor current zero crossing. Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below 1.5V (30% of VCC). VRHOT is high impedance in shutdown. Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge the BST_-LX_ flying capacitor during the times the respective DL_s are high. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 1F or greater ceramic capacitor. Phase 1 Low-Side Gate-Driver Output. DL1 swings from GND to VDD. DL1 is forced low in shutdown. DL1 is forced high when an output overvoltage fault is detected, overriding any negative currentlimit condition that might be present. DL1 is forced low in skip mode after detecting an inductor current zero crossing. Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also used as an input to phase 1's zero-crossing comparator. Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 highside gate driver. An internal switch between VDD and BST1 charges the BST1-LX1 flying capacitor while the low-side MOSFET is on (DL1 pulled high). Power-Good Logic Input Pin that Indicates the Power Status of Other System Rails and Used for Supply Sequencing. During startup, after soft-starting to the boot voltage, the output voltage remains at VBOOT, and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGD_IN input stays low. When PGD_IN later goes high, the output is allowed to transition to the voltage set by the VID code, and CLKEN is allowed to go low. During normal operation, if PGD_IN goes low, the controller immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in skip mode at 1/4 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until the controller is turned off or power cycled, or until PGD_IN goes high again. Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0-D6 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the logic-level voltages on D0-D6 (see Table 4). The 1111111 code corresponds to a shutdown mode. When this code is detected, The MAX17030/MAX17036 initiate a soft-shutdown transition identical to the shutdown transition for a SHDN falling edge. After slewing the output to 0V, it forces DH_, DL_, and DRSKP low, and three-states PWM3. The IC remains active and its VCC quiescent current consumption stays the same as in normal operation. If D6-D0 is changed from 1111111 to a different code, the MAX17030/MAX17036 initiate a startup sequence identical to the startup sequence for a SHDN rising edge. Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
MAX17030/MAX17036
21
BST2
22 23
LX2 DH2
24
DL2
25
VRHOT
26
VDD
27
DL1
28 29
DH1 LX1
30
BST1
31
PGD_IN
32-38
D0-D6
39
CSP1
______________________________________________________________________________________
15
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Pin Description (continued)
PIN NAME FUNCTION Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. A 10 discharge FET is turned on in UVLO event or thermal shutdown, or at the end of soft-shutdown. Exposed Backplate (Pad) of Package. Internally connected to both analog ground and power (driver) grounds. Connect to the ground plane through a thermally enhanced via.
RTON 200k CIN NH CBST L1 R3 OUTPUT (IMVP-6.5 CORE) COUT
40
CSN1
--
PAD (GND)
32 33 34 VID INPUTS 35 36 37 38 ON OFF (VRON) DPRSLPVR PGDIN PSI 5V BIAS RVCC 20 CVCC 1.0F CVDD 2.2F 7 13 14 31 15 26
D0 D1 D2 D3 D4 D5 D6 SHDN DPRSLPVR PGDIN PSI VDD
TON
16
30 BST1 28 DH1 LX1 DL1 CSP1 29 27 39 2 40 21 23 22 24 12 2 11 CCS2 CBST CCS1
8V TO 20V PWR INPUT
NL
R1
R2
RNTC1
CSN1 BST2 DH2
8V TO 20V PWR INPUT CIN NH L2 R6
VCC ILIM TIME
MAX17030 MAX17036
LX2 DL2 CSP2
NL
R4
COUT
5 RILIM1 RILIM2 6
R5
RNTC2
CSN2 3.3V VCCP RVRHOT 56 RCLKEN 1.9k RPWRGD 1.9k 18 25 17 IMON RIMON VSS_SENSE VCC RTHRM 13k NTC 100k = 4250 PAD 3 THRM CSN3 FBAC FB GNDS 4 PWRGD VRHOT CLKEN IMON DRSKP CSP3
5V BIAS CVCC1 1.0F VCC BST DH CBST NH L3 CIN
8V TO 20V PWR INPUT
MAX8791
PWM3 20 19 2 2 1 9 8 10 CCS3 RFB CFBS 1000pF RFBS 10 PWM SKIP
LX DL GND R8 RNTC3 NL R7 R9 COUT
VCC_SENSE RGNDS 10 VSS_SENSE
RCATCHCORE 10 CPU REMOTE SENSE
CGNDS 4700pF
RCATCHGND 10
Figure 1. Standard 3-Phase IMVP-6.5 Application Circuit
16 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Table 1. Component Selection for Standard Applications
DESIGN PARAMETERS Circuit Input Voltage Range Maximum Load Current Transient Load Current Load Line POC Setting TON Resistance (RTON) Inductance (L) IMVP-6.5 XE CORE 3-PHASE Figure 1 8V to 20V 65A (48A TDC) 49A (100A/s) -1.9mV/A 110 200k (f SW = 300kHz) IMVP-6.5 SV CORE 3-PHASE Figure 1 8V to 20V 52A (38A TDC) 39A (100A/s) -1.9mV/A 101 200k (f SW = 300kHz) IMVP-6.5 SV CORE 2-PHASE Figure 2 8V to 20V 52A (38A TDC) 39A (100A/s) -1.9mV/A 101 200k (f SW = 300kHz)
0.36H, 36A, 0.82m (10mm x 10mm) Panasonic ETQP4LR36ZFC Fairchildsemi 1x FDS6298 9.4m /12m (typ/max) Toshiba 1x TPCA8030-H 9.6m /13.4m (typ/max)
0.42H, 20A, 1.55m (7mm x 7mm) NEC/TOKIN MPC0740LR42C Fairchildsemi 1x FDS6298 9.4m /12m (typ/max) Toshiba 1x TPCA8030-H 9.6m /13.4m (typ/max Fairchildsemi 1x FDS8670 4.2m /5m (typ/max) Toshiba 1x TPCA8019-H 3x 330F, 2V, 4.5m Panasonic EEFSXOD331E4 or NEC/Tokin PSGVOE337M4.5 27x 22F, 6.3V X5R ceramic capacitor (0805) 4x 10F 25V ceramic (1210) 14k 137k 453k 10.2k
0.36H, 36A, 0.82m (10mm x 10mm) Panasonic ETQP4LR36ZFC Fairchildsemi 1x FDS6298 9.4m /12m (typ/max) Toshiba 1x TPCA8030-H 9.6m /13.4m (typ/max) Fairchildsemi 2x FDS8670 4.2m /5m (typ/max) Toshiba 2x TPCA8019-H 4x 330F, 6m , 2.5V Panasonic EEFSX0D0D331XR 28x 10F, 6V ceramic (0805) 4x 10F 25V ceramic (1210) 16.9k 133k 6.04k 14k
High-Side MOSFET (NH)
Fairchildsemi 2x FDS8670 Low-Side MOSFET (NL) 4.2m /5m (typ/max) Toshiba 2x TPCA8019-H 4x 330F, 2V, 4.5m Output Capacitors (COUT) Panasonic EEFSXOD331E4 or (MAX17030 Only) NEC/Tokin PSGVOE337M4.5 Contact Maxim for MAX17036 27x 22F, 6.3V X5R reference design ceramic capacitor (0805) Input Capacitors (CIN) TIME-ILIM Resistance (RILIM2) ILIM-GND Resistance (RILIM1) FB Resistance (RFB) IMON Resistance (RIMON) LX-CSP Resistance CSP-CSN Resistance DCR Sense NTC (RNTC) DCR Sense Capacitance (CSENSE) 6x 10F 25V ceramic (1210) 14k 137k 6.04k 12.1k 2.21k 3.24k 40.2k (R1, R4, R7) (R2, R5, R8) (R3, R6, R9)
1.4k
(R1, R4, R7)
2.21k 3.24k 40.2k
(R1, R7) (R2, R8) (R3, R9)
2k (R2, R5, R8) 40.2k (R3, R6, R9) 10k NTC B = 3380 TDK NTCG163JH103F 0.22F, 6V ceramic (0805)
10k NTC B = 3380 TDK NTCG163JH103F 0.22F, 6V ceramic (0805)
10k NTC B = 3380 TDK NTCG163JH103F 0.22F, 6V ceramic (0805)
______________________________________________________________________________________
17
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Table 2. Component Suppliers
MANUFACTURER AVX Corp. Fairchild Semiconductor NEC/TOKIN America, Inc. Panasonic Corp. SANYO Electric Co., Ltd. WEBSITE www.avxcorp.com www.fairchildsemi.com www.nec-tokinamerica.com www.panasonic.com www.sanyodevice.com MANUFACTURER Siliconix (Vishay) Taiyo Yuden TDK Corp. TOKO America, Inc. Toshiba America Electronic Components, Inc. WEBSITE www.vishay.com www.t-yuden.com www.component.tdk.com www.tokoam.com www.toshiba.com/taec
32 33 34 VID INPUTS 35 36 37 38 ON OFF (VRON) DPRSLPVR PGDIN PSI 5V BIAS RVCC 20 CVCC 1.0F RILIM1 RILIM2 CVDD 2.2F 13 14 31
D0 D1 D2 D3 D4 D5 D6 SHDN DPRSLPVR PGDIN
TON BST1 DH1 LX1 DL1
16 30 28 29 27
RTON 200k CIN NH CBST L1 R3
8V TO 20V PWR INPUT
OUTPUT (IMVP-6.5 CORE) COUT
NL
R1
CSP1
39 2 40 21 23 NH CBST R7 L2 R9 CCS1 8V TO 20V PWR INPUT CIN R2 RNTC1
15 PSI 26 VDD
CSN1 BST2
7
VCC
5 6
MAX17030 DH2 MAX17036 22
LX2 DL2 24
ILIM TIME
NL
COUT
3.3V VCCP RVRHOT 56 RCLKEN 1.9k RPWRGD 1.9k 18 25 17 IMON RIMON VSS_SENSE VCC RTHRM 13k NTC 100k = 4250 PAD 3 THRM 4
CSP2
12 2 CCS2
R8
RNTC3
CSN2 PWRGD VRHOT CLKEN IMON CSP3 CSN3 FBAC FB GNDS PWM3 DRSKP
11 20 19 2 1 9 8 10
5V BIAS RCATCHCORE 10 RFB CFBS 1000pF RGNDS 10 RFBS 10 VCC_SENSE VSS_SENSE RCATCHGND 10 CPU REMOTE SENSE
Figure 2. Standard 2-Phase IMVP-6.5 Application Circuit
18 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
THRM VRHOT PHASE 3 DRIVER CONTROL CSN3 0.3 x VCC Q CSP3 10x CSN3 ONE-SHOT PHASE 3 ON-TIME TON CC13 Gm(CCI) CSP2 10x CSN2 PHASE 2 DRIVERS TRIG TRIG3 Gm(CCI) CSP3 CSP1 CSN1 BST2 DH2 LX2 DL2 GND PWM3 DRSKP
CSP1 10x CSN1 ILIM TIME MINIMUM OFF-TIME Q VCC REF (2.0V) GND D0-D6 PGDIN SHDN DAC R-TO-I CONVERTER SLEW TRIG
Q
TRIG CC12 CSN2 TRIG 3 Gm(CCI) CSP2 CSP1 CSN1 TON R Q S MAIN PHASE DRIVERS BST1 DH1 LX1
ONE-SHOT PHASE 2 ON-TIME
ONE SHOT PHASE 1 ON-TIME ONE-SHOT Q TRIG FB
Gm(CCI)
PGND1 TARGET FAULT PHASE SEL LX1 0mV
S Q R VDD
SKIP DL1 TARGET - 300mV FB 5ms STARTUP DELAY SKIP 60s CSP CSN CSP CSN x3 IMON Gm(IMON) CLKEN TARGET + 200mV GND PWRGD
GNDS
x3 FBAC Gm(FB)
MAX17030 MAX17036
MODE/PHASE/SLEWRATE CONTROL
BLANK
PGDIN DPRSLPVR
PSI
Figure 3. Functional Diagram
______________________________________________________________________________________ 19
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Detailed Description
Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 3). This architecture relies on the output filter capacitor's ESR to act as the currentsense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a oneshot whose period is inversely proportional to input voltage, and directly proportional to output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot section). Another oneshot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley currentlimit threshold, and the minimum off-time one-shot times out. The controller maintains 120 out-of-phase operation by alternately triggering the three phases after the error comparator drops below the output-voltage set point. VIN and VDD can be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
Switching Frequency (TON)
Connect a resistor (RTON) between TON and VIN to set the switching period TSW = 1/fSW, per phase: TSW = 16.26pF x (RTON + 6.5k) A 96.75k to 303.25k corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively. High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of component size and board space.
TON Open-Circuit Protection
The TON input includes open-circuit protection to avoid long, uncontrolled on-times that could result in an overvoltage condition on the output. The MAX17030/ MAX17036 detect an open-circuit fault if the TON current drops below 10A for any reason--the TON resistor (RTON) is unpopulated, a high resistance value is used, the input voltage is low, etc. Under these conditions, the MAX17030/MAX17036 stop switching (DH and DL pulled low) and immediately set the fault latch. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller.
Triple 120 Out-of-Phase Operation
The three phases in the MAX17030/MAX17036 operate 120 out-of-phase to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count--reducing cost, board space, and component power requirements--making the MAX17030/MAX17036 ideal for high-power, cost-sensitive applications. The MAX17030/MAX17036 share the current between three phases that operate 120 out-of-phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of each phase is effectively reduced, resulting in reduced input voltage ripple, ESR power loss, and RMS ripple current (see the Input Capacitor Selection section). Therefore, the same performance can be achieved with fewer or less-expensive input capacitors.
+5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95% efficient +5V system supply. The +5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is:
IBIAS = ICC + fSW Q G(LOW) + Q G(HIGH)
On-Time One-Shot The MAX17030/MAX17036 contain a fast, low-jitter, adjustable one-shot that sets the high-side MOSFETs on-time. It is shared among the three phases. The oneshot for the main phase varies the on-time in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB):
T ( V + 0.075V ) t ON = SW FB VIN The one-shot for the second phase and third phase varies the on-time in response to the input voltage and the difference between the main and the other inductor currents. Two identical transconductance amplifiers integrate the difference between the master and each slave's current-sense signals. The summed output is connected to an internal integrator for each masterslave pair, which serves as the input to the respective slave's high-side MOSFET TON timer.
(
)
where ICC is provided in the Electrical Characteristics table, fSW is the switching frequency, and QG(LOW) and Q G(HIGH) are the MOSFET data sheet's total gatecharge specification limits at VGS = 5V.
20
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
When the main and other phase current-sense signals (VCM = VCMP - VCMN and VCS = VCSP - VCSM) become unbalanced, the transconductance amplifiers adjust the other phase's on-time, which increases or decreases the phase inductor current until the current-sense signals are properly balanced:
V + 0.075V t ON(SEC) = TSW CCI VIN V + 0.075V ICCIZ CCI 7 = TSW FB + TSW V VIN IN
including MOSFET, inductor, and PCB resistances; VCHG is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time as determined above.
MAX17030/MAX17036
Current Sense
The MAX17030/MAX17036 sense the output current of each phase allowing the use of current-sense resistors on inductor DCR as the current-sense element. Lowoffset amplifiers are used for current balance, voltagepositioning gain, and current limit. Using the DC resistance (RDCR) of the output inductor allows higher efficiency. The initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage droop-error budget and current monitor. This current-sense method uses an RC filtering network to extract the current information from the output inductor (see Figure 4). The RC network should match the inductor's time constant (L/RDCR): R2 R CS = R R1 + R2 DCR and: R CS = L 1 1 + C EQ R1 R2
= (Main On-time) + ( Secondary Current Balance Correction) t
where V CCI is the internal integrator node for each slave's current-balance integrator, and Z CCI is the effective impedance at that node. During phase overlap, t ON is calculated based on phase 1's on-time requirements, but reduced by 33% when operating with three phases. For a 3-phase regulator, each phase cannot be enabled until the other 2 phases have completed their on-time and the minimum off-times have expired. As such, the minimum period is limited by 3 x (t ON + tOFF(MIN)). Maximum tON is dependent on minimum VIN and maximum output voltage: TSW(MIN) = NPH x (tON(MAX) + tOFF(MIN)) where: tON(MAX) = VFB(MAX)/VIN(MIN x TSW(MIN) so: TSW(MIN) = tOFF(MIN)/[1/NPH - VIN(MAX)/VIN(MIN)] Hence, for a 7V input and 1.1V output, 500kHz is the maximum switching frequency. Running at this limit is not desirable as there is no room to allow the regulator to make adjustments without triggering phase overlap. For a 3-phase, high-current application with minimum 8V input, the practical switching frequency is 300kHz. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by parasitics in the conduction paths and propagation delays. For loads above the critical conduction point, where the dead-time effect (LX flying high and conducting through the high-side FET body diode) is no longer a factor, the actual switching frequency (per phase) is: fSW = t ON ( VIN + VDIS - VCHG )
( VOUT + VDIS )
where RCS is the required current-sense resistance, and RDCR is the inductor's series DC resistance. Use the typical inductance and RDCR values provided by the inductor manufacturer. To minimize the currentsense error due to the current-sense inputs' bias current (ICSP_ and ICSN_), choose R1//R2 to be less than 2k and use the above equation to determine the sense capacitance (CEQ). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage Positioning and Loop Compensation section for detailed information. When using a current-sense resistor for accurate output-voltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (L ESL ) of the currentsense resistor (see Figure 4). The ESL induced voltage step might affect the average current-sense voltage. The RC filter's time constant should match the LESL/ R SENSE time constant formed by the current-sense resistor's parasitic inductance: L ESL = C EQR EQ R SENSE
21
where VDIS and VCHG are the sum of the parasitic voltage drops in the inductor discharge and charge paths,
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
INPUT (VIN) CIN
DH_ LX_
NH SENSE RESISTOR L LESL RSENSE COUT LESL RSENSE
MAX17030 DL_ MAX17036
NL
DL
CEQREQ =
REQ CSP_ CSN_
CEQ
A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) CIN
DH_ LX_
NH INDUCTOR L RDCR RCS = NL DL COUT R1 R2 RDCR = L 11 + CEQ R1 R2 R2 RDCR R1 + R2
MAX17030 DL_ MAX17036
[
]
CSP_ CSN_
CEQ FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR
B) LOSSLESS INDUCTOR SENSING
Figure 4. Current-Sense Methods
where LESL is the equivalent series inductance of the current-sense resistor, RSENSE is current-sense resistance value, and CEQ and REQ are the time-constant matching components.
IOS(IBAL) = ILMAIN - ILSEC =
VOS(IBAL) R SENSE
Current Balance
The MAX17030/MAX17036 integrate the difference between the current-sense voltages and adjust the ontime of the secondary phase to maintain current balance. The current balance relies on the accuracy of the current-sense signals across the current-sense resistor or inductor DCR. With active current balancing, the current mismatch is determined by the current-sense resistor or inductor DCR values and the offset voltage of the transconductance amplifiers:
22
where R SENSE = R CM = R CS and V OS(IBAL) is the current balance offset specification in the Electrical Characteristics table. The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency.
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
Current Limit The current-limit circuit employs a unique "valley" current-sensing algorithm that senses the voltage across the current-sense resistors or inductor DCR at the current-sense inputs (CSP_ to CSN_). If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current of the selected phase drops below the valley current-limit threshold. When any one phase exceeds the current limit, all phases are effectively current limited since the interleaved controller does not initiate a cycle with the next phase. Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the currentsense resistance, inductor value, and battery voltage. The positive valley current-limit threshold voltage at CSP to CSN equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). Connect ILIM directly to VCC to set the default current-limit threshold setting of 22.5mV (typ). The negative current-limit threshold (forced-PWM mode only) is nominally -125% of the corresponding valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately activates an on-time pulse--DL turns off, and DH turns on--allowing the inductor current to remain above the negative current threshold. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP_, CSN_).
amplifier's output current (IFB) is determined by the sum of the current-sense voltages: IFB = Gm(FB) VCSX
X =1 PH
MAX17030/MAX17036
where VCSX = VCSP - VCSN is the differential currentsense voltage, and G m(FB) is typically 400S as defined in the Electrical Characteristics.
Differential Remote Sense The MAX17030/MAX17036 include differential, remotesense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor's power pins. The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (RFB) and ground sense (GNDS) input directly to the processor's remote sense outputs as shown in Figure 1. Integrator Amplifier An internal integrator amplifier forces the DC average of the FB voltage to equal the target voltage, allowing accurate DC output-voltage regulation regardless of the output ripple voltage.
The MAX17030/MAX17036 disable the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode (DPRSLPVR = high). The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier (Steady-State Droop) The MAX17030/MAX17036 include a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier's input is generated by summing the current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor's DCR. The amplifier's output connects directly to the regulator's voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltage-positioning gain:
VOUT = VTARGET - R FBIFB where the target voltage (VTARGET) is defined in the Nominal Output Voltage Selection section, and the FB
Transient Overlap Operation
When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 120 out-ofphase when a transient occurs actually respond slower than an equivalent single-phase controller. In order to provide fast transient response, the MAX17030/ MAX17036 support a phase overlap mode, which allows the triple regulators to operate in-phase when heavy load transients are detected, effectively reducing the response time. After any high-side MOSFET turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on all high-side MOSFETs with the same on-time during the next on-time cycle. The phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum
23
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
off-time expires. The on-time for each phase is based on the input voltage to FB ratio (i.e., follows the master on-time), but reduced by 33% in a 3-phase configuration, and not reduced in a 2-phase configuration. This maximizes the total inductor current slew rate. After the phase-overlap mode ends, the controller automatically begins with the next phase. For example, if phase 2 provided the last on-time pulse before overlap operation began, the controller starts switching with phase 3 when overlap operation ends.
Nominal Output Voltage Selection
The nominal no-load output voltage (V TARGET ) is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VFB = VDAC + VGNDS where VDAC is the selected VID voltage. On startup, the MAX17030/MAX17036 slew the target voltage from ground to the preset boot voltage. Table 3 is the operating mode truth table.
DAC Inputs (D0-D6) The digital-to-analog converter (DAC) programs the output voltage using the D0-D6 inputs. D0-D6 are low-voltage (1.0V) logic inputs, designed to interface directly with the CPU. Do not leave D0-D6 unconnected. Changing D0-D6 initiates a transition to a new output-voltage level. Change D0-D6 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect DAC readings might cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with the IMVP-6.5 (Table 4) specifications. OFF Code VID = 1111111 is defined as an OFF code. When the OFF code is set, the MAX17030/MAX17036 go through the same shutdown sequence as though SHDN has been pulled low--output discharged to zero, CLKEN high, and PWRGD low. Only the IC supply currents remain at the operating levels rather than the shutdown level. When exiting from the OFF code, the MAX17030/ MAX17036 go through the boot sequence, similar to the sequence when SHDN is first pulled high.
Table 3. Operating Mode Truth Table
INPUTS SHDN GND DPRSLPVR X PSI X PHASE OPERATION* Disabled Multiphase Pulse Skipping 1/4 RTIME Slew Rate Multiphase Forced-PWM Nominal RTIME Slew Rate (N-1)-Phase Forced-PWM Nominal RTIME Slew Rate OPERATING MODE Low-Power Shutdown Mode. DL1 and DL2 forced low, and the controller is disabled. The supply current drops to 1A (max). Startup/Boot. When SHDN is pulled high, the MAX17030/ MAX17036 begin the startup sequence. Once the REF is above 1.84V, the controller enables the PWM controller and ramps the output voltage up to the boot voltage. See Figure 9. Full Power. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). Intermediate Power. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). When PSI is pulled low, the MAX17030/MAX17036 immediately disable phase 3, PWM3 is three-state, and DRSKP is low. Deeper Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (D0-D6, Table 4). When DPRSLPVR is pulled high, the MAX17030/MAX17036 immediately enter 1-phase pulseskipping operation allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked. DH2 and DL2 are pulled low, PWM3 is three-state and DRSKP is low.
Rising
X
X
High
Low
High
High
Low
Low
High
High
X
1-Phase Pulse Skipping Nominal RTIME Slew Rate
*Multiphase operation = All enabled phases active.
24
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Table 3. Operating Mode Truth Table (continued)
INPUTS SHDN DPRSLPVR PSI PHASE OPERATION* OPERATING MODE Shutdown. When SHDN is pulled low, the MAX17030/MAX17036 immediately pull PWRGD low, CLKEN becomes high impedance, all enabled phases are activated, and the output voltage is ramped down to 12.5mV; then DH and DL are pulled low and CSNI discharge FET is turned on. Fault Mode. The fault latch has been set by the MAX17030/MAX17036 UVP or thermal-shutdown protection, or by the OVP protection. The controller remains in fault mode until VCC power is cycled or SHDN toggled.
Falling
X
X
Multiphase Forced-PWM 1/4 RTIME Slew Rate
High
X
X
Disabled
*Multiphase operation = All enabled phases active.
Table 4. IMVP-6.5 Output Voltage VID DAC Codes
D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875
______________________________________________________________________________________
25
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Table 4. IMVP-6.5 Output Voltage VID DAC Codes (continued)
D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT VOLTAGE (V) 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0 0 0 0 0 0 0 Off
26
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
Suspend Mode When the processor enters low-power deeper sleep mode, the IMVP-6.5 CPU sets the VID DAC code to a lower output voltage and drives DPRSLPVR high. The MAX17030/MAX17036 respond by slewing the internal target voltage to the new DAC code, switching to singlephase operation, and letting the output voltage gradually drift down to the deeper sleep voltage. During the transition, the MAX17030/MAX17036 blank both the upper and lower PWRGD and CLKEN thresholds until 20s after the internal target reaches the deeper sleep voltage. Once the 20s timer expires, the MAX17030/ MAX17036 reenable the lower PWRGD and CLKEN threshold, but keep the upper threshold blanked.
The average inductor current per phase required to make an output-voltage transition is: IL C OUT x (dVTARGET dt ) TOTAL
MAX17030/MAX17036
where dVTARGET/dt is the required slew rate, COUT is the total output capacitance, and TOTAL is the number of active phases.
Output-Voltage-Transition Timing
At the beginning of an output-voltage transition, the MAX17030/MAX17036 blank both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the lower PWRGD threshold approximately 20s after the slew-rate controller reaches the target output voltage, but the upper PWRGD threshold is enabled only if the controller remains in forced-PWM operation. If the controller enters pulse-skipping operation, the upper PWRGD threshold remains blanked. The slew rate (set by resistor RTIME) must be set fast enough to ensure that the transition can be completed within the maximum allotted time. The MAX17030/MAX17036 automatically control the current to the minimum level required to complete the transition. The total transition time depends on RTIME, the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (tTRAN) is given by: t TRAN = VNEW - VOLD (dVTARGET dt )
Deeper Sleep Transitions When DPRSLPVR goes high, the MAX17030/MAX17036 immediately disable phases 2 and 3 (DH2, DL2 forced low, PWM3 three-state, DRSKP low), and enter pulseskipping operation (see Figures 5 and 6). If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target still ramps as before, and PWRGD remains blanked high impedance until 20s after the output voltage reaches the internal target. Once this time expires, PWRGD monitors only the lower threshold:
* Fast C4E Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage still exceeds the deeper sleep voltage, the MAX17030/MAX17036 quickly slew (50mV/s min regardless of RTIME setting) the internal target voltage to the DAC code provided by the processor as long as the output voltage is above the new target. The controller remains in skip mode until the output voltage equals the internal target. Once the internal target reaches the output voltage, phase 2 is enabled. The controller blanks PWRGD and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 5. Standard C4 Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while the output voltage is regulating to the deeper sleep voltage, the MAX17030/MAX17036 immediately activate all enabled phases and ramp the output voltage to the LFM DAC code provided by the processor at the slew rate set by RTIME. The controller blanks PWRGD and CLKEN (forced high impedance) until 20s after the transition is completed. See Figure 6.
*
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate, VOLD is the original output voltage, and VNEW is the new target voltage. See TIME Slew-Rate Accuracy in the Electrical Characteristics for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/4.
______________________________________________________________________________________
27
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
ACTUAL VOUT CPU CORE VOLTAGE VID (D0-D6) DPRSLPVR PSI INTERNAL PWM CONTROL DH1 DH2 PWM3 PWRGD CLKEN OVP BLANK HIGH-Z BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK HIGH THRESHOLD ONLY SET TO 1.5V MIN BLANK HI-Z BLANK LO TRACKS INTERNAL TARGET DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE) NO PULSES: VOUT > VTARGET FORCED-PWM INTERNAL TARGET DEEPER SLEEP VID
tBLANK 20s typ
tBLANK 20s typ
Figure 5. C4E (C4 Early Exit) Transition
ACTIVE VID CPU CORE VOLTAGE VID (D0-D6) DPRSLPVR PSI INTERNAL PWM CONTROL DH1 DH2 PWM3 PWRGD BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HIGH-Z BLANK LOW DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE) NO PULSES: VOUT > VTARGET FORCED-PWM INTERNAL TARGET ACTUAL VOUT LFM VID DPRSLP VID LFM VID
DEEPER SLEEP VID
CLKEN
BLANK LOW
BLANK HIGH THRESHOLD ONLY
OVP
SET TO 1.5V MIN tBLANK 20s TYP
TRACKS INTERNAL TARGET tBLANK 20s TYP
Figure 6. Standard C4 Transition
28 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
PSI Transitions When PSI is pulled low, the MAX17030/MAX17036 immediately disable phase 3 (PWM3 three-state, DRSKP forced low) and enter 2-phase PWM operation (see Figure 7). When PSI is pulled high, the MAX17030/ MAX17036 enable phase 3.
Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the processor can switch the controller to a low-power pulse-skipping control scheme by entering suspend mode. PSI determines how many phases are active when operating in forced-PWM mode (DPRSLPVR = low). When PSI is pulled low, phases 1 and 2 remain active but phase 3 is disabled (PWM3 three-state, DRSKP forced low).
MAX17030/MAX17036
Forced-PWM Operation (Normal Mode)
During soft-shutdown and normal operation--when the CPU is actively running (DPRSLPVR = low, Table 5)-- the MAX17030/MAX17036 operate with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gatedrive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors.
Light-Load Pulse-Skipping Operation (Deeper Sleep)
During soft-start and normal operation when DPRSLPVR is pulled high, the MAX17030/MAX17036 operate with a single-phase pulse-skipping mode. The pulse-skipping mode enables the driver's zero-crossing comparator, so the controller pulls DL1 low when its current-sense inputs detect "zero" inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under lightload conditions to avoid overcharging the output.
CPU FREQ
CPU LOAD
VID (D0-D6)
CPU CORE VOLTAGE PSI DH1 DH2 PWM3 PWRGD CLKEN BLANK HIGH-Z BLANK LOW 180 OUT-OF-PHASE tBLANK 20s typ tBLANK 20s typ PWM3 THREE-STATE
BLANK HIGH-Z BLANK LOW
Figure 7. PSI Transition
______________________________________________________________________________________ 29
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
When pulse-skipping, the controller blanks the upper PWRGD and CLKEN thresholds. Upon entering pulseskipping operation, the controller temporarily sets the OVP threshold to 1.5V, preventing false OVP faults when the transition to pulse-skipping operation coincides with a VID code change. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code. The MAX17030/MAX17036 automatically use forced-PWM operation during soft-start and soft shutdown, regardless of the DPRSLPVR and PSI configuration. low duty cycles. The total load-current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately: T V V - VOUT ILOAD(SKIP) = SW OUT IN 2 x VIN L
Power-Up Sequence (POR, UVLO)
The MAX17030/MAX17036 are enabled when SHDN is driven high (Figure 9). The reference powers up first. Once the reference exceeds its undervoltage-lockout (UVLO) threshold, the internal analog blocks are turned on and masked by a 150s one-shot delay. The PWM controller then begins switching.
Automatic Pulse-Skipping Switchover In skip mode (DPRSLPVR = high), an inherent automatic switchover to PFM takes place at light loads (Figure 8). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs. Once VLX drops below the zero-crossing comparator threshold (see the Electrical Characteristics), the comparator forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-topeak ripple current, which is a function of the inductor value (Figure 8). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically
INDUCTOR CURRENT
V - VOUT I = IN t L
IPEAK
ILOAD = IPEAK/2
0 ON-TIME TIME
Figure 8. Pulse-Skipping/Discontinuous Crossover Point
VCC
SHDN IGNORE VID IGNORE VID SOFT-SHUTDOWN 1/4 SLEW RATE SET BY RTIME
VID (D0-D6) SOFT-START 1/4 SLEW RATE SET BY RTIME VCORE INTERNAL PWM CONTROL
PULSE-SKIPPING
FORCED-PWM
CLKEN IMVPOK tBLANK 60s TYP tBLANK 20s TYP tBLANK 5ms TYP tBLANK 20s TYP
Figure 9. Power-Up and Shutdown Sequence Timing Diagram
30 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC is above 4.25V, and SHDN driven high. With the reference in regulation, the controller ramps the output voltage to the boot voltage (1.1V) at 1/4 the slew rate set by RTIME: t TRAN(START) =
Current Monitor (IMON)
The MAX17030/MAX17036 include a unidirectional transconductance amplifier that sources current proportional to the positive current-sense voltage. The IMON output current is defined by: IIMON = Gm(IMON) x (VCSP - VCSN) where Gm(IMON) = 1.6mS (typ) and the IMON current is unidirectional (sources current out of IMON only) for positive current-sense values. For negative currentsense voltages, the IMON current is zero. Connect an external resistor between IMON and GNDS to create the desired IMON gain based on the following equation: RIMON = 0.9V/(IMAX x RSENSE(MIN) x Gm(IMON_MIN)) where IMAX is defined in the Current Monitor section of the Intel IMVP-6.5 specification and based on discrete increments (10A, 20A, 30A, 40A, etc.), RSENSE(MIN) is the minimum effective value of the current-sense element (sense resistor or inductor DCR) that is used to provide the current-sense voltage, and Gm(IMON_MIN) is the minimum transconductance amplifier gain as defined in the Electrical Characteristics. The IMON voltage is internally clamped to a maximum of 1.1V (typ), preventing the IMON output from exceeding the IMON voltage rating even under overload or short-circuit conditions. When the controller is disabled, IMON is pulled to ground. The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot directly drive large capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 1.
MAX17030/MAX17036
(dVTARGET
4VBOOT
dt )
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. CLKEN is pulled low approximately 60s after the MAX17030/MAX17036 reach the boot voltage. At the same time, the MAX17030/MAX17036 slew the output to the voltage set at the VID inputs at the programmed slew rate. PWRGD becomes high impedance approximately 5ms after CLKEN is pulled low. The MAX17030/ MAX17036 automatically operate in pulse-skipping mode during soft-start, and use forced-PWM operation during soft-shutdown, regardless of the DPRSLPVR and PSI configuration. If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions, and shuts down immediately. DH and DL are forced low, and CSNI 10 discharge FET is enabled.
Shutdown
When SHDN goes low, the MAX17030/MAX17036 enters low-power shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down at 1/4 the slew rate set by RTIME: t TRAN(SHDN) = 4VOUT dVTARGET dt ) (
Temperature Comparator (VRHOT)
The MAX17030/MAX17036 also feature an independent comparator with an accurate threshold (V HOT ) that tracks the analog supply voltage (VHOT = 0.3VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistordivider between VCC and GND to generate a voltageregulator overtemperature monitor. Place the thermistor as close to the MOSFETs and inductors as possible.
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate. After the output voltage drops to 12.5mV, the MAX17030/MAX17036 shut down completely--the drivers are disabled (DL1 and DL2 driven low, PWM3 is three-state, and DRSKP low), the reference turns off, 10 CSNI discharge FET is turned on, and the supply current drops below 1A. When an undervoltage fault condition activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V.
Fault Protection (Latched)
Output Overvoltage Protection The overvoltage-protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17030/MAX17036 continuously monitor the output for an overvoltage fault. An OVP fault is detected if the output voltage exceeds the set VID DAC voltage by more than 300mV, or the fixed 1.5V (typ) threshold
31
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
during a downward VID transition in skip mode. During pulse-skipping operation (DPRSLPVR = high), the OVP threshold tracks the VID DAC voltage as soon as the output is in regulation; otherwise, the fixed 1.5V (typ) threshold is used. When the OVP circuit detects an overvoltage fault while in multiphase mode (DPRSLPVR = low, PSI = high), the MAX17030/MAX17036 immediately force DL1 and DL2 high, PWM3 low, and DRSKP high; and pull DH1 and DH2 low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. When an overvoltage fault occurs while in 1-phase operation (DPRSLPVR = high, or PSI = low), the MAX17030/MAX17036 immediately force DL1 high and pull DH1 low. DL2 and DH2 remain low as phase 2 was disabled. DL2 does not react. Overvoltage protection can be disabled through the nofault test mode (see the No-Fault Test Mode section).
MAX17030/MAX17036
No-Fault Test Mode The latched fault-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a "no-fault" test mode is provided to disable the fault protection--overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate drivers (DH) source 2.7A and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH_ floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST_, while the DL_ synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. A low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates is required for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17030/MAX17036 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The DL low on-resistance of 0.25 (typ) helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. The capacitive coupling between LX and DL created by the MOSFET's gate-to-drain capacitance (CRSS), gateto-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold to prevent shoot-through currents: C VGS(TH) > VIN(MAX) RSS CISS Adding a 4700pF between DL and power ground (CNL in Figure 10), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays.
Output Undervoltage Protection If the MAX17030/MAX17036 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the fault latch. Once the output voltage ramps down to 12.5mV, it forces the DL1 and DL2 low and pulls DH1 and DH2 low, three-states PWM3, and sets DRSKP low 10 CSNI discharge FET is turned on. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller.
UVP can be disabled through the no-fault test mode (see the No-Fault Test Mode section).
Thermal-Fault Protection The MAX17030/MAX17036 feature a thermal fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor sets the fault latch and forces the DL1 and DL2 low and pulls DH1 and DH2 low, three-states PWM3, sets DRSKP low, and enables 10 CSNI discharge FET on. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C.
Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section).
32
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
*
BST_ (RBST)* INPUT (VIN) CBST DH_ LX_ NH L
CBYP VDD
Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: I ILOAD(PHASE) = LOAD TOTAL where TOTAL is the total number of active phases.
MAX17030/MAX17036
DL_ (CNL)* PGND
NL
MAX17030/MAX17036
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENT.
*
Figure 10. Gate Drive Circuit
Shoot-through currents can also be caused by a combination of fast high-side MOSFETs and slow low-side MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (R BST in Figure 10). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 30% and 50% ripple current. for a multiphase core regulator, select an LIR value of ~0.4.
*
Multiphase Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency.
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: VOUT VIN - VOUT L = TOTAL fSWILOAD(MAX)LIR VIN where TOTAL is the total number of phases.
______________________________________________________________________________________
33
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must not to saturate at the peak inductor current (IPEAK): ILOAD(MAX) LIR IPEAK = 1+ 2 TOTAL
Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
f fESR SW where: fESR = and: R EFF = R ESR + R DROOP + R PCB where COUT is the total output capacitance, RESR is the total equivalent series resistance, RDROOP is the voltage-positioning gain, and RPCB is the parasitic board resistance between the output capacitors and sense resistors. For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, SANYO POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR zero frequencies below 50kHz. In the standard application circuit, the ESR needed to support a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5m. Four 330F/2.5V Panasonic SP (type SX) capacitors in parallel provide 1.5m (max) ESR. With a 2m droop and 0.5m PCB resistance, the typical combined ESR results in a zero at 30kHz. Ceramic capacitors have a high ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. When using only ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value favors high switching-frequency operation with small inductor values to minimize the energy transferred from inductor to capacitor during load-step recovery. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output-voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. 1 2R EFF C OUT
Output Capacitor Selection
Output capacitor selection is determined by the controller stability requirements, and the transient soar and sag requirements of the application.
Output Capacitor ESR The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
(RESR + RPCB ) I
VSTEP
LOAD(MAX)
The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. When operating multiphase systems out-of-phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For multiphase operation, the maximum ESR to meet ripple requirements is: VINfSWL R ESR VRIPPLE ( VIN - TOTAL VOUT ) VOUT where TOTAL is the total number of active phases and fSW is the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section).
34
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast 10% to 90% max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The multiphase Quick-PWM controllers operate out-ofphase, reducing the RMS input. For duty cycles less than 100%/OUTPH per phase, the IRMS requirements can be determined by the following equation:
ILOAD IRMS = TOTAL VOUT ( VIN - TOTAL VOUT ) TOTAL VIN
MAX17030/MAX17036
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. For a dual-phase controller, the worst-case output sag voltage can be determined by: TMIN VSAG x 2 TOTAL C OUT VOUT KTSW - TMIN and: TMIN = t ON + t OFF(MIN) L ILOAD(MAX)
where TOTAL is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with V IN = 2TOTALVOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD/TOTAL. Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters.
(
)2
High-Side MOSFET Power Dissipation The conduction loss in the high-side MOSFET (NH) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage:
V I PD (NH Resistive) = OUT LOAD R DS(ON) VIN TOTAL where TOTAL is the total number of phases. Calculating the switching losses in the high-side MOSFET (NH) is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: V I f Q G(SW) PD (NH Switching) = IN LOAD SW TOTAL IGATE C V 2f + OSS IN SW 2 where COSS is the NH MOSFET's output capacitance, Q G(SW) is the charge needed to turn on the N H MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ).
35 2
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics), T SW is the programmed switching period, and TOTAL is the total number of active phases. K = 66% when NPH = 3, and K = 100% when NPH = 2. VSAG must be less than the transient droop ILOAD(MAX) x RDROOP. The capacitive soar voltage due to stored inductor energy can be calculated as: VSOAR
( ILOAD(MAX) ) 2 L
2 TOTAL C OUT VOUT
where TOTAL is the total number of active phases. The actual peak of the soar voltage is dependent on the time where the decaying ESR step and rising capacitive soar is at its maximum. This is best simulated or measured. For the MAX17036 with transient suppression, contact Maxim directly for application support to determine the output capacitance requirement.
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
The optimum high-side MOSFET trades the switching losses with the conduction (RDS(ON)) losses over the input voltage range. Ideally, the losses at V IN(MIN) should be roughly equal to losses at VIN(MAX) , with lower losses in between. If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (1) FDS6298 n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single FDS6298 has a maximum gate charge of 19nC (VGS = 5V). Using the above equation, the required boost capacitance would be: C BST = 1 x 10nC = 0.05F 200mV
Low-Side MOSFET Power Dissipation For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
2 V I PD (NL Resistive) = 1- OUT LOAD R DS(ON) V IN(MAX) TOTAL
Selecting the closest standard value; this example requires a 0.1F ceramic capacitor.
The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit can be overdesigned to tolerate: I ILOAD = TOTAL I VALLEY(MAX) + INDUCTOR 2 ILOAD(MAX)LIR = TOTALI VALLEY(MAX) + 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-size heatsink to handle the overload power dissipation. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two thermally enhanced 8-pin SOs), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-todrain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur (see the MOSFET Gate Drivers section). The optional Schottky diode (DL) should have a low forward voltage and be able to handle the load current per phase during the dead times.
Current Limit and Slew-Rate Control (TIME and ILIM)
TIME and ILIM are used to control the slew rate and current limit. TIME regulates to a fixed 2.0V. The MAX17030/MAX17036 use the TIME source current to set the slew rate (dVTARGET/dt). The higher the source current, the faster the output-voltage slew rate: 71.5k dVTARGET dt = 12.5mV s x R TIME where RTIME is the sum of resistance values between TIME and ground. The ILIM voltage determines the valley current-sense threshold. When ILIM = VCC, the controller uses the 22.5mV preset current-limit threshold. In an adjustable design, ILIM is connected to a resistive voltagedivider connected between TIME and ground. The differential voltage between TIME and ILIM sets the current-limit threshold (VLIMIT), so the valley current-sense threshold: V - VILIM VLIMIT = TIME 10 This allows design flexibility since the DCR sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mV. Keeping VLIMIT between 20mV to 40mV leaves room for future current-limit adjustment. The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: LIR I VALLEY > ILOAD(MAX) 1 - 2
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high-side MOSFETs' gates: C BST =
36
N x Q GATE 200mV
______________________________________________________________________________________
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
where: I VALLEY = VLIMIT R SENSE 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 2) Connect all analog grounds to a separate solid copper plane, which connects to the ground pin of the Quick-PWM controller. This includes the VCC bypass capacitor, FB, and GNDS bypass capacitors. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCB (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. 4) Keep the high current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. 5) CSP_ and CSN_ connections for current limiting and voltage positioning must be made using Kelvin sense connections to guarantee the current-sense accuracy. 6) When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. 7) Route high-speed switching nodes away from sensitive analog areas (FB, CSP_, CSN_, etc.).
MAX17030/MAX17036
where RSENSE is the sensing resistor or effective inductor DCR.
Voltage Positioning and Loop Compensation
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power-dissipation requirements. The MAX17030/MAX17036 use a transconductance amplifier to set the transient and DC output voltage droop (Figure 3) as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated.
Steady-State Voltage Positioning Connect a resistor (RFB) between FB and VOUT to set the DC steady-state droop (load line) based on the required voltage-positioning slope (RDROOP):
R FB = R DROOP R SENSEGm(FB)
where the effective current-sense resistance (RSENSE) depends on the current-sense method (see the Current Sense section), and the voltage positioning amplifier's transconductance (G m(FB) ) is typically 400S as defined in the Electrical Characteristics table. The controller sums together the input signals of the currentsense inputs (CSP_, CSN_). When the inductors' DCR is used as the current-sense element (RSENSE = RDCR), each current-sense input should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, C IN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50mils to 100mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the controller IC.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Refer to the MAX17030 Evaluation Kit specification for a layout example and follow these guidelines for good PCB layout:
______________________________________________________________________________________
37
1/2/3 Phase-Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036
4) Make the DC-DC controller ground connections as shown in the standard application circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the highpower components go; the power ground plane, where the GND pin and VDD bypass capacitor go; the master's analog ground plane, where sensitive analog components, the master's GND pin and VCC bypass capacitor go; and the slave's analog ground plane, where the slave's GND pin and VCC bypass capacitor go. The master's GND plane must meet the GND plane only at a single point directly beneath the IC. Similarly, the slave's GND plane must meet the GND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the highpower output ground with a short metal trace from GND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4055-2 DOCUMENT NO. 21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX17030GTL

	To Download MAX17030GTL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .